Company Synopsys
Website www.synopsys.com
Eligibility BE/BTech
Experience Freshers
Location Bengalore
Job Role engineer (Technical)
JOB SUMMARY:
Company Profile:
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software,
IP and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of
implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and
manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
Job Description:
1. The selected intern candidate will be part of the IP verification/ VIP team in Solutions Group, Synopsys , India and be
based at Bangalore.
2. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ Vera in a
VMM environment in one of the following domain :USB3/USB2/Ethernet/MIPI
3. The intern will be taken through hands-on training in Verification methodologies such as VMM and in the respective
domain.
4. Subsequent to training, the nature of work would be on the following lines:
5. Understanding product architecture for VIP or Test environment, coding in one of the HVL such as System Verilog,
Website www.synopsys.com
Eligibility BE/BTech
Experience Freshers
Location Bengalore
Job Role engineer (Technical)
JOB SUMMARY:
Company Profile:
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software,
IP and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of
implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and
manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
Job Description:
1. The selected intern candidate will be part of the IP verification/ VIP team in Solutions Group, Synopsys , India and be
based at Bangalore.
2. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ Vera in a
VMM environment in one of the following domain :USB3/USB2/Ethernet/MIPI
3. The intern will be taken through hands-on training in Verification methodologies such as VMM and in the respective
domain.
4. Subsequent to training, the nature of work would be on the following lines:
5. Understanding product architecture for VIP or Test environment, coding in one of the HVL such as System Verilog,
Verification of the blocks that are coded, understanding and implementing functional coverage infrastructure. It will involve
closely working as part of the product development team.
Candidate Profile:
1. The candidate must have completed Bachelors degree in computers/electronics/ Electrical engg with minimum 70% or 7.0 CGPA.
2. Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above.
Requirements:
1. Candidates with good problem solving skills and kknowledge of HDL such as Verilog with strong concepts in OOPs and
C++.
2. Exposure to HVL Languages such as SystemVerilog/Vera/SpecmanE is highly preferable.
3. Aptitude to work in VLSI Verification domain is a must and only those who are willing to put it extra effort and take up
technical challenges need apply.
click here to apply
click here to apply
